STA Lead, Physical Design Engineer

Overview

Role involves STA timing analysis for high-speed CPU core design.

Ideal candidate should have hands-on ASIC timing experience and expertise in timing EDA tools.

Locations

• United States

Requirements

• Degree in EE, EECS or CS required
• Hands-on ASIC timing experience
• Expertise in timing EDA tools required
• Proficient in scripting languages
• Ability to work cross-functionally
• Strong problem-solving skills required

Responsibilities

• Conduct full chip timing analysis
• Develop timing methodologies
• Generate timing constraints
• Analyze scenarios with design team
• Collaborate with physical design teams

Benefits

• Competitive compensation package
• Equal opportunity employer