Senior Member of Technical Staff

Overview

Role involves implementing and optimizing block level components in SoC design.

Ideal candidate should have 3+ years of experience in SoC design with expertise in PnR and timing analysis.

Locations

• United States, Texas, Austin

Requirements

• Master's in Electronics, Electrical, or Computer Engineering
• 3 years of experience
• 1 year in PnR flow
• 1 year in timing analysis
• 1 year in optimizing floor plans
• 1 year in clock distribution networks
• 1 year in automation scripting
• 1 year in full chip timing analysis

Responsibilities

• Implement block level subcomponents
• Optimize floor plans
• Analyze and close timing
• Run physical verification
• Contribute to PnR automation
• Design high frequency clock networks
• Design high performance interfaces
• Generate physical and timing constraints