Verification Designer

Overview

Role involves developing and executing verification plans for electronic designs.

Ideal candidate should have 3+ years of digital verification experience and proficiency in SystemVerilog or VHDL.

Locations

• United States

Requirements

• Bachelor's degree required
• At least 3 years of experience in digital verification
• Proficient in SystemVerilog and/or VHDL

Responsibilities

• Develop and execute verification plans
• Design and implement verification test-benches
• Perform functional and performance verification
• Debug and resolve design issues
• Generate and maintain documentation
• Enhance verification process and methodologies